A power gating method that suspends power supply to a certain circuit block for the purpose of reducing power consumption in a semiconductor device is known in the art (see Patent Document 1, for example). Further, a technology to apply a bias voltage to the back gate of a transistor is known in the art (see Patent Documents 2, 3, and 4, for example).
[Patent Document 1] Japanese Laid-open Patent Publication No. 2008-300696
[Patent Document 2] Japanese Laid-open Patent Publication No. 2001-230664
[Patent Document 3] Japanese Laid-open Patent Publication No. 2008-103927
[Patent Document 4] Japanese Laid-open Patent Publication No. H7-212217